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Application Note 1159
The OC trip point varies mainly due to the MOSFET’s
the external feedback resistor (R2) and the external resistor
r DS(ON) variations. To avoid overcurrent tripping in the
normal operating load range, calculate the R OCSET resistor
from the equation above using:
tied to VMSET (R6).
TABLE 2.
1. The maximum R DS(ON) at the highest junction
temperature.
2. The minimum I OCSET from the specification table.
GPIO1
L
L
GPIO2
L
H
VOUT
No Change
+ Delta VOUT
Determine I PEAK for I PEAK > I OUT ( MAX ) + ( ? I ) ? 2
,
H
L
- Delta VOUT
where ? I is the output inductor ripple current. A small
H
H
Ignored
ceramic capacitor should be placed in parallel with R OCSET
to smooth the voltage across R OCSET in the presence of
switching noise on the input voltage.
The overcurrent trip point on the evaluation board has been
set to 18A. Figure 7 shows the overcurrent hiccup mode.
Transient Performance
Figure 8 shows the response of the output when subjected
to transient loading from 10mA to 10A.
The evaluation board has a 330k ? VMSET resistor (R6)
setting a current:
IVM = 2.468V/330k ? = 7.48μA
and
V(delta) = 7.48μA*20.5k ? = 0.153V
Figure 8 shows the output voltage in voltage margining
mode for various VMSET resistor values.
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
150
175
200
225
250
275
300
325
350
375
400
RVMSET (k ? )
FIGURE 8. TRANSIENT RESPONSE
Voltage Margining
Voltage margining mode is enabled by connecting a
margining set resistor (R6) from the VMSET pin to ground.
This resistor to ground will set a current, which is switched to
the FB pin. The current will be equal to 2.468V divided by the
value of the external resistor tied to the VMSET pin.
The GPIO1 (P8) and GPIO2 (P7) pins control the current
switching as per Table 2 below. The power supply output
increases when GPIO2 is HIGH and decreases when GPIO1
is HIGH. Using a jumper to short the pins of JP2 and JP3 will
pull GPIO1 and GPIO2 LOW. Remove these jumpers to pull
GPIO1 or GPIO2 HIGH for voltage margining. The amount
that the output voltage of the power supply changes with
voltage margining will be equal to 2.468V times the ratio of
4
FIGURE 9. CHANGE IN OUTPUT VOLTAGE FOR VARIOUS
RESISTORS
The slew time of the current is set by an external capacitor
(C13) on the CDEL pin, which is charged and discharged
with a 100μA current source. The change in voltage on the
capacitor is 2.5V. This same capacitor is also used to set the
PGOOD rise delay. When PGOOD is low, the internal
PGOOD circuitry uses the capacitor and when PGOOD is
high the voltage margining circuit uses the capacitor. The
slew time for voltage margining can be in the range of 300μs
to 2.5ms. The CDEL capacitor on the evaluation board is
0.1μF leading to a voltage margining slew rate of 2.5ms.
AN1159.0
November 10, 2004
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